1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having memory cells each including a three-dimensional capacitor suitable for the purpose of attaining a higher integration level.
2. Description of the Prior Art
FIG. 6 is a sectional view showing a memory cell portion of a conventional semiconductor memory device, which is a stack-type DRAM.
The stack-type DRAM comprises a semiconductor substrate 61 on which switching transistors 65 are formed, each switching transistor 65 being connected to a stacked capacitor 100 and a bit line 70.
Each of the switching transistors 65 is a MOS transistor, and is formed on each element region (active region) of the semiconductor substrate 61. The respective element regions are surrounded by an isolating oxide film 62a so that they are electrically isolated from one another.
The switching transistor 65 comprises a source region 63 and a drain region 64 both formed in the semiconductor substrate 61, and also comprises a gate electrode 66 disposed between the source region 63 and the drain region 64 and slightly above the semiconductor substrate 61. Between the gate electrode 66 and the semiconductor substrate 61 is disposed a gate insulating film 62b. The top and sides of the gate electrode 66 are covered with an insulating film 62c.
The stacked capacitor 100 comprises a storage electrode 67, a cell plate 69, and a capacitor insulating film 68 interposed therebetween.
The source region 63 of the switching transistor 65 is in contact with the storage electrode 67, while the drain region 64 of the switching transistor 65 is in contact with the bit line 70.
An insulating film 62d covers all the above-mentioned elements, lines, etc., formed on the semiconductor substrate 61.
In this DRAM, electric carriers are accumulated and stored in the storage electrode 67 of the capacitor 100.
When the switching transistor 65 is turned on, the electric carriers stored in the capacitor 100 are delivered from the storage electrode 67 into the source region 63, and then transmitted through the portion of the semiconductor substrate 61 below the gate electrode 66, and through the drain region 64, and then into the bit line 70.
As the switching transistor 65 is turned on or off, writing of data to the capacitor 100 or reading of data therefrom is executed.
FIG. 7 is a sectional view showing a memory cell portion of another conventional semiconductor memory device, which is a stacked trench-type DRAM.
The stacked trench-type DRAM comprises an IVEC (Isolation-Merged Vertical Capacitor) memory cell structure.
This stacked trench-type DRAM (IVEC-DRAM) comprises a semiconductor substrate 71 on which switching transistors 75 are formed, each switching transistor 75 being connected to a capacitor 200 and a bit line 80.
Each of the switching transistors 75 is a MOS transistor and is formed on each element region 81 of the semiconductor substrate 71. The respective element regions 81 are surrounded by a trench 82 so that they are electrically isolated from one another.
The switching transistor 75 comprises a source region 73 and a drain region 74 both formed in the semiconductor substrate 71, and also comprises a gate electrode 75 disposed between the source region 73 and the drain region 74 and slightly above the semiconductor substrate 71. Between the gate electrode 76 and the semiconductor substrate 71 is interposed a gate insulating film 72b. The top and sides of the gate electrode 76 are covered with a gate insulating film 72c.
The stacked trench-type DRAM of FIG. 7 is different from the stack-type DRAM of FIG. 6 in the structure of the capacitor 200, as will be described below.
The capacitor 200 shown in FIG. 7 is disposed within the trench 82 formed in the semiconductor substrate 71. The capacitor 200 comprises a storage electrode 77, a cell plate 79, and a capacitor insulating film 78 interposed therebetween, all of which are electrically isolated from the semiconductor substrate 71 by means of an insulating film 72a formed on the bottom and sides of the trench 82.
The source region 73 of the switching transistor 75 is in contact with the storage electrode 77 disposed in the trench 82, while the drain region 74 of the switching transistor 75 is in contact with the bit line 80.
In this DRAM, electric carriers are accumulated and stored in the capacitor 200.
When the switching transistor 75 is turned on, the electric carriers stored in the capacitor 200 are delivered from the storage electrode 77 into the source region 73, and then transmitted through the portion of the semiconductor substrate 71 below the gate electrode 76, and through the drain region 74, and then into the bit line 80.
As the switching transistor 75 is turned on or off, writing of data to the capacitor 200 or reading of data therefrom is executed.
The stack-type DRAM is described in more detail by H. Watanabe et al., in "Stacked Capacitor Cells for High-density dynamic RAMs; IEDM Dig. of Tech. papers (1988), p. 600". The trench-type DRAM is described in more detail by Shigeru Nakajima et al., in "An Isolation-Merged Vertical Capacitor Cell for Large Capacity DRAM; IEDM Dig. of Tech. Papers (1988), p. 240".
Conventional DRAMs of the above-mentioned types have the following problems:
In the stack-type DRAM shown in FIG. 6, as the memory cells become smaller in size and spaces therebetween become narrower for attaining a higher integration level, the area of the storage electrode 67 of the capacitor 100 is reduced, thereby decreasing the capacitance thereof.
The IVEC-DRAM shown in FIG. 7 also involves the above-mentioned problem. In the IVEC-DRAM, if the depth of the trench 82 is increased, the area of the storage electrode 77 of the capacitor 200 can be enlarged to attain larger capacitance. However, since it is difficult to produce a semiconductor memory device having a deeper trench, the increase in the depth of the trench will cause a great reduction in the yield of the memory devices.